1. Field of the Invention
The present invention relates to a process for producing semiconductor devices, and more particularly to improvements in forming an impurity diffused region (hereinafter referred to as a "well") as isolated to provide therein components of a semiconductor device. The production process of the present invention is useful as a process for fabricating semiconductor devices of high integration which are low in well resistance.
2. Background of the Invention
In producing semiconductor devices, the well is formed usually by the step of introducing impurities into a semiconductor substrate from its surface side as by ion implantation, and a diffusion step which involves heating for a prolonged period of time.
With bipolar semiconductor devices, especially bipolar CMOS devices, it is required to reduce the collector resistance by lowering the well resistance, especially the internal resistance of the well.
However, when the well is formed only by diffusing impurities from the surface side of the substrate as stated above, the impurity concentration of the substrate surface is limited (usually to about 10.sup.16 atoms/cm.sup.3 if highest) to inherently set an upper limit on the well concentration, consequently presenting difficulties in lowering the well resistance to not higher than 700 to 2000 ohms/cm.sup.2 in terms of sheet resistance. As the complexity of CMOS devices increases, therefore, there arises the problem of impaired latchup resistance.
With semiconductor devices of the type mentioned, accordingly, the well resistance is reduced by forming an impurity diffused region of high concentration in the form of a buried layer, then forming an epitaxial layer, and thereafter introducing and diffusing impurities into the epitaxial layer to form a well of (buried) double-layer structure.
Further such buried wells are isolated by utilizing PN junctions or by a selective oxidation process termed the LOCOS process. Presently the LOCOS process is generally employed since the isolation resorting to PN junctions encounters difficulties in fabricating semiconductor devices of higher density with higher operating speed.
Bipolar semiconductor devices are produced by the above conventional process, for example, through the steps to be described below with reference to FIG. 5a to FIG. 5h.
First as shown in FIG. 5a, an N.sup.+ layer (buried layer) 152 having a high impurity concentration is formed in a P-type silicon substrate 151 using a resist layer (or silicon oxide layer) 153 as a mask.
Next as seen in FIG. 5b, a P-type epitaxial layer 154 is grown, which is further doped with N-type impurities by ion injection and thermal diffusion to form an N.sup.- well 155 as shown in FIG. 5c. The well is then isolated by the LOCOS process as seen in FIG. 5d. Indicated at 156 is a LOCOS oxide film.
A P-type base region 157 is formed in the N.sup.- well 155 as shown in FIG. 5e. Next, a high-concentration N-type layer (collector contact portion) 158 is formed for connection to collector wiring as shown in FIG. 5f. Further as shown in FIG. 5g, a high-concentration P-type layer (base contact portion) 159 is formed for connection to base wiring. Finally as shown in FIG. 5h, an emitter region 160 is formed, followed by connection of base wiring 161, emitter wiring 162 and collector wiring 163 to the base contact portion 159, emitter region 160 and collector contact portion 158, respectively.
The above process wherein the buried well is used realizes a reduction in well resistance, but requires cumbersome time-consuming steps such as formation of the buried layer and epitaxial growth, consequently making the semiconductor device costly. The process has another problem in that the defects that could occur in the epitaxial layer would lead to a lower yield.
Additionally with the LOCOS process which is widely utilized for well isolation, the well isolation zone becomes enlarged, for example, owing to the occurrence of so-called bird's beak in the form of a laterally developed oxide film, consequently presenting difficulties in providing semiconductor devices of higher complexity. Further in the case where well isolation is to be accomplished by the LOCOS process in the fabrication of bipolar semiconductor devices, the required isolation dielectric strength can not be obtained unless the well isolation width is considerably large. FIGS. 6 (a) and (b) show that well isolation by the LOCOS process requires an isolation: width of about 6 to about 10 micrometers.
To overcome the problem encountered in well isolation, Unexamined Japanese Patent Publication SHO 63-1045 discloses a method of effecting well isolation by forming a trench in the well isolation zone and burying an insulating material in the trench. The publication SHO 63-1045 states that the method achieves a great decrease in the width of well isolation zone and that the trench is usable also for forming memory capacitors ("A VARIABLE-SIZE SHALLOW TRENCH ISOLATION (STI) TECHNOLOGY WITH DIFFUSED SIDEWALL DOPING FOR SUBMICRON CMOS," CH2528-8/88, 92-95-IEDM 88, IEEE (1988); NEW EFFECTS OF TRENCH ISOLATED TRANSISTOR USING SIDE-WALL GATES," CH2515-5/87, 736-739-IEDM 87, IEEE (1987)). However, there has not been any case wherein such a trench is utilized for forming wells.